With progress of miniaturization and cost reduction of semiconductor devices, miniaturization of a structure near electrode pads of semiconductor chips is also desired. Meanwhile, the number of electrode pads tends to increase due to multi-functionalization of the semiconductor devices.
In recent years, often used is a structure in which a lower layer wiring in a semiconductor chip and an electrode pad are electrically connected together through a via.
Incidentally, the structure in which the electrode pad of the semiconductor chip and the lower layer wiring are electrically connected through the via is disclosed in, for example, Japanese Patent Application Laid-open No. 2002-16069 (Patent Document 1) and Japanese Patent Application Laid-open No. 11-126790 (Patent Document 2).